1. Technical Field
One or more embodiments of the present disclosure generally relates to the electronics field. In particular, the disclosure relates to connections of electronic devices.
2. Description of the Related Art
Each electronic device typically comprises one or more chips (for example, of semiconductor material), each one of which is provided with terminals for its connection to external circuits.
According to a typical connection mode, the chip is encapsulated within an insulating body having exposed leads for connection to a printed circuit board (PCB); the terminals of the chip are connected to respective leads by bonding wires.
However, the bonding wires involve an increase of size of the electronic device, and introduce resistive, capacitive and/or inductive parasitisms (having values being not predictable a priori) that impair performance thereof. Furthermore, the bonding wires involve long production processes (as they should be welded serially) and burdensome designs (configurations avoiding short-circuits between the bonding wires).
According to another connection mode (called “flip chip”), the chip is mounted upside down onto the PCB (or onto a chip carrier), so that its terminals contact the PCB directly (or by conductive balls of the chip carrier, connected to the terminals of the chip through via-holes thereof). In this way, the absence of the bonding wires allows obtaining electronic devices having small size and high performance.
However, the “flip chip” connection mode has drawbacks that preclude a wider use thereof, e.g., in case of a chip having terminals exposed on different surfaces of it (such as in electronic devices for power applications). In such case, in fact, before mounting the chip onto the PCB (or onto the chip carrier), it is necessary to carry out operations for making all its terminals accessible by a same side thereof.
For example, in case of a vertical-structure power transistor with a lower terminal (drain terminal) and two upper terminals (gate and source terminals), such operations comprise: fixing of the chip onto an electrically conductive base plate (with the drain terminal in contact with the base plate), forming of an insulating layer onto the chip and onto a portion of the base plate being not covered by the chip (for example, by electrolytic growth), making of the through-holes through the insulating layer for exposing the gate terminal, the source terminal and the portion of the base plate (for example, by etching), and metalling of the through-holes for contacting the gate terminal, the source terminal and the base plate (and hence the drain terminal). In this way, the gate and source terminals and the drain terminal are accessible, through respective contacts, on a same surface, thus making it possible the flip chip connection onto the PCB (or onto the chip carrier) through them. However, such operations involve an excessive duration of the production process of the electronic device, and involve practical and constructive inefficiencies as well.
In particular, the making of the through-holes is typically performed in several phases (as they have different depths), and it exposes the chip to perforations risks.